1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to an EPROM (Erasable Programmable ROM (Read Only Memory)) formed within a single chip microcomputer and associated with a read-inhibiting circuit for protecting a content of the EPROM.
2. Description of Related Art
An EPROM is widely used for development and evaluation of a program to be written in a masked ROM which is mainly used in articles manufactured on a mass production basis, and also for an initial mass production stage of articles. Therefore, the EPROM is written with information, such as know-how of a program, which should be kept secret from outsiders. However, since a content of the EPROM can easily be read by a PROM writer, it has become necessary to provide a memory protection circuit for the EPROM for the purpose of protecting the information written in the EPROM.
Japanese Patent Post-examination Publication No. Showa 61-28144 proposed a conventional example of the memory protection circuit for the EPROM. The memory protection circuit disclosed in this Japanese patent publication is shown in FIG. 1.
As shown in FIG. 1, this EPROM memory protection circuit is provided for an erasable ROM (EPROM) 301 including a number of memory cells which are of the FAMOS (floating gate avalanche injection MOS (metal-oxide-semiconductor)) structure and which are arranged in the form of a matrix. A plurality of output signal lines 302 extend from the EPROM 301.
The EPROM memory protection circuit includes a read-inhibiting flag 303 composed of an EPROM cell of the FAMOS structure which is provided separately from the EPROM 301 and which is written through a writing line 304, and a read-inhibiting circuit composed of a two-input AND gates 306 of the number corresponding to the number of the output signal lines 302 extending from the EPROM 301. Each of the two-input AND gates 306 has its one input connected to a corresponding one of the output signal lines 302 of the EPROM 301 and its other input connected in common to an output signal line 305 of the read-inhibiting flag 303. A port 307 is connected to respective output signal lines of the two-input AND gates 306.
Now, operation of the EPROM memory protection circuit shown in FIG. 1 will be explained.
1. In the case where the reading of the EPROM 301 is inhibited.
In order to inhibit the reading of the EPROM 301, the read-inhibiting flag 303 is preliminarily written through the writing line 304, so that the value of the output signal line 305 of the read-inhibiting flag 303 is brought to a logical low level signal "L". The outputs of the EPROM 301 are applied to the read-inhibiting AND gates 306 through the signal lines 302. Here, since the value of the signal line 305, which is supplied to the one input of each of the two-input AND gates 306 (constituting the read-inhibiting circuit), is at the logical low level "L", the output of all the two-input AND gates 306 are fixed to the logical low level "L", and therefore, the wading of the EPROM 301 from an external is inhibited.
2. In the case where the reading of the EPROM 301 is permitted.
In order to permit the reading of the EPROM 301, the read-inhibiting flag 303 is kept at an initial value, so that the value of the output signal line 305 of the read-inhibiting flag 303 is brought to a logical high level "H". The outputs of the EPROM 301 are applied through the signal lines 302 to the read-inhibiting AND gates 306. Since the value of the signal line 305, which is supplied to the one input of the two-input AND gates 306 (constituting the read-inhibiting circuit), is at the logical high level "H", the output of each two-input AND gate is made identical to a corresponding output of the EPROM 301, and send out to the external through the port 307. In this way, the output of the EPROM 301 is permitted.
Accordingly, after the reading of the EPROM 301 has been inhibited by the EPROM memory protection circuit, the reading of the content of the EPROM 301 needs erasure of the read-inhibiting flag 303. If ultraviolet ray are irradiated so as to erase the read-inhibiting flag 303 composed of the EPROM cell, the data stored in the EPROM 301 will also be inevitably erased simultaneously. Namely, when the EPROM 301 is put in a condition allowing its reading as the result of erasure of the read-inhibiting flag 303, the data to be read has already been erased. Accordingly, there is finally no concern that the data might be read from the external.
However, the above mentioned conventional EPROM memory protection circuit has the following problems.
1. Essentially, it is often the case that a user tries to confirm the content of a specific area of the EPROM even after the reading has been inhibited. For example, the reading of a program written in the EPROM should be inhibited, while data written in the EPROM should be able to be read out. PA1 2. In the above mentioned conventional EPROM memory protection circuit, a third person who attempts to mad the program is inhibited from reading the content of the EPROM from an external by using an EPROM writer or the like. Therefore, when the information of the EPROM is read from the external, since there is a sharp distinction between the reading inhibition and the reading permission in the conventional method, it is a problem that it can be immediately known that the EPROM is in a read-inhibiting condition. PA1 3. In addition, since the read-inhibiting flag 303 is provided separately from the EPROM 301, both a circuit structure and a mask design of a chip become complicated. Furthermore, since the read-inhibiting circuit composed of the AND gates 306 is provided near the output port, and since the control signals 305 are wired or extended to the proximity of the output port, it is a problem that the wiring area on a chip increases.
In the above mentioned conventional example of the EPROM memory protection circuit, however, the reading from the external is inhibited for the whole area corresponding to all bits of the EPROM. Therefore, it is impossible to partially inhibit the reading. For this reason, there is a serious problem that the reading is inhibited even in the area from which the reading inhibition is not desired by the user.